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K9F1G08U0A

Samsung semiconductor
Part Number K9F1G08U0A
Manufacturer Samsung semiconductor
Description FLASH MEMORY
Published Apr 7, 2005
Detailed Description ELECTRONICS March. 2003 San 16 Banwol-Ri Taean-Eup Hwasung- City Kyungki Do, Korea Tel.) 82 - 31 - 208 - 6463 Fax.) 82...
Datasheet PDF File K9F1G08U0A PDF File

K9F1G08U0A
K9F1G08U0A

Overview
ELECTRONICS March.
2003 San 16 Banwol-Ri Taean-Eup Hwasung- City Kyungki Do, Korea Tel.
) 82 - 31 - 208 - 6463 Fax.
) 82 - 31 -208 - 6799 1Gb 1.
8V NAND Flash Errata Description : Some of AC characteristics are not meeting the specification.
> AC characteristics : Refer to Table Affected Products : K9F1G08Q0M-YCB0/YIB0, K9F1G16Q0M-YCB0/YIB0 K9K2G08Q0M-YCB0/YIB0, K9K2G16Q0M-YCB0/YIB0 Improvement schedule : The components targeted to meet the specification is scheduled to be available by workweek 25 along with the final specification values.
Workaround : Relax the relevant timing parameters according to the table.
Table Parameters Specification Relaxed Condition tWC 45 80 tWH 15 20 tWP 25 60 tRC 50 80 tREH 15 20 tRP 25 60 UNIT : ns tREA 30 60 tCEA 45 75 Sincerely, chwoosun@sec.
samsung.
com Product Planning & Application Eng.
Memory Division Samsung Electronics Co.
1 K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY Document Title 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory Revision History Revision No 0.
0 0.
1 History 1.
Initial issue 1.
Iol(R/B) of 1.
8V is changed.
- min.
value : 7mA --> 3mA - Typ.
value : 8mA --> 4mA 2.
AC parameter is changed.
tRP(min.
) : 30ns --> 25ns 3.
A recovery time of minimum 1µs is required before internal circuit gets ready for any command sequences as shown in Figure 17.
---> A recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 17.
Draft Date July.
5.
2001 Nov.
5.
2001 Remark Advance Dec.
4.
2001 0.
2 1.
ALE status fault in ’ Random data out in a page’ timing diagram(page 19) is fixed.
1.
tAR1, tAR2 are merged to tAR.
(Page11) (Before revision) min.
tAR1 = 10ns , min.
tAR2 = 50ns (After revision) min.
tAR = 10ns 2.
min.
tCLR is changed from 50ns to 10ns.
(Page11) 3.
min.
tREA is changed from 35ns to 30ns.
(Page11) 4.
min.
tWC is changed from 50...


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