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C5001

International
Part Number C5001
Manufacturer International
Description Low Skew Muliple Frequency PCI Clock Generator with EMI Reducing SSCG
Published Apr 22, 2005
Detailed Description C5001 Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG. Approved Product Product Features S S S S ...
Datasheet PDF File C5001 PDF File

C5001
C5001

Overview
C5001 Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG.
Approved Product Product Features S S S S S S S S S S S S Produces PCI output clocks that are individually 2 selectable for 33.
3 or 66.
6 MHz under I C or strapping control.
Separate output buffer power supply for reduced noise, crosstalk and jitter.
input clock frequency standard 14.
31818 MHz Output clocks frequency individually selectable via 2 I C or hardware bi-directional pin strapping.
SSCG EMI reduction at 1.
0% width 2 Individual clock disables via I C control All output clocks skewed within a 500 pS window Cycle to Cycle jitter ± 250 pS Output duty cycle is automatically 50% (±10%) adjusted Clock feed through mode and OE pins for logic testing Glitchless clock enabling and disabling transitions 28-pin TSSOP or SSOP package Output Enable logic Functionality Table OE CLK(0:9) PLL 1 (HIGH) Enabled Running 0 (LOW) Tri State Running Block Diagram XIN XOUT Reference Oscillator ÷1 ÷2 M U X Pin Configuration REFCLK0/S0 CLK1/S1 ÷1 ÷2 ÷1 ÷2 VDD CLK2/S2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16.
15 VDD1 REF-CLK0/S0 CLK1/S1 VSS VDD2 CLK2/S2 CLK3/S3 VSS VDD3 CLK4/S4 CLK5/S5 VSS VDD4 CLK6/S6 XIN XOUT VSS OE SCLK SDATA VSS VSS CLK9/S9 CLK8/S8 VDD5 VSS CLK7/S7 PLL ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 CLK3/S3 CLK4/S4 CLK5/S5 CLK6/S6 CLK7/S7 CLK8/S8 OE SDATA SCLK I2C LOGIC ÷1 ÷2 ÷4, ÷8 CLK9/S9 INTERNATIONAL MICROCIRCUITS, INC.
525 LOS COCHES ST.
MILPITAS, CA 95035.
TEL: 408-263-6300.
FAX 408-263-6571 Rev.
2.
1 6/14/1999 Page 1 of 13 C5001 Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG.
Approved Product Pin Description Pin Number 2 Pin Name XIN PWR VDDA I/O I Description This pin is the connection point for the devices Loop reference frequency.
This may be either a CMOS 3.
3 volt reference clock or the output of an external crystal.
A nominal 14.
31818 MHz frequency must be supplied to obtain the frequencies listed on this da...


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