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NT5DS64M4AW

Nanya
Part Number NT5DS64M4AW
Manufacturer Nanya
Description (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM
Published Sep 24, 2006
Detailed Description www.DataSheet4U.com NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333/300 SDRAM Features CAS Latency and Fr...
Datasheet PDF File NT5DS64M4AW PDF File

NT5DS64M4AW
NT5DS64M4AW


Overview
www.
DataSheet4U.
com NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333/300 SDRAM Features CAS Latency and Frequency CAS Latency 2 2.
5 Maximum Operating Frequency (MHz)* DDR333 (-6) DDR300 (-66) 133 133 166 150 • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions.
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2, 2.
5 • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes • 7.
8µs Maximum Average Periodic Refresh Interval • 2.
5V (SSTL_2 compatible) I/O • VDDQ = 2.
5V ± 0.
2V • VDD = 2.
5V ± 0.
2V • Package : 66pin TSOP-II / 60 balls 0.
8mmx1.
0mm pitch CSP.
Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations.
An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double data rate As with standard SDRAMs, the pipelined, multibank architecarchitecture is essentially a 2n prefetch architecture with an ture of DDR SDRAMs allows for concurrent operation, interface designed to transfer two data words per clock cycle thereby providing high effective bandwidth by hiding row preDataSheet4U.
com DataShee at the I/O pins.
A single read or write access for the 256Mb charge and activation time.
DDR SDRAM eff...


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