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NT5DS64M4BS

Nanya Techology
Part Number NT5DS64M4BS
Manufacturer Nanya Techology
Description (NT5DSxxMxBx) 256Mb DDR SDRAM
Published Sep 24, 2006
Detailed Description www.DataSheet4U.com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS...
Datasheet PDF File NT5DS64M4BS PDF File

NT5DS64M4BS
NT5DS64M4BS

Overview
www.
DataSheet4U.
com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 3 2.
5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2.
5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.
8µs Maximum Average Periodic Refresh Interval SSTL_2 compatible I/O interface VDDQ = 2.
6V ± 0.
1V VDD = 2.
6V ± 0.
1V Lead-free and Halogen-free product available Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecThe 256Mb DDR SDRAM uses a double-data-rate architecture of DDR SDRAMs allows for concurrent operation, ture to achieve high-speed operation.
The double data rate thereby providing high effective bandwidth by hiding row prearchitecture is essentially a 2n prefetch architecture with an charge and activation time.
interface designed to transfer two data words per clock cycle DataSheet4U.
com An auto refresh mode is provided along with a power-saving DataShee at the I/O pins.
A single read or write access for the 256Mb Po...


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