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NT5DS32M16AF

Part Number	NT5DS32M16AF
Manufacturer	Nanya Techology
Description	(NT5DSxxMxAF) 512Mb DDR SDRAM
Published	Sep 24, 2006
Detailed Description	www.DataSheet4U.com NT5DS128M4AF NT5DS64M8AF NT5DS32M16AF 512Mb DDR SDRAM Features CAS Latency and Frequency CAS Latenc...
Datasheet	NT5DS32M16AF PDF File

Overview

www.
DataSheet4U.
com NT5DS128M4AF NT5DS64M8AF NT5DS32M16AF 512Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 2 2.
5 Maximum Operating Frequency (MHz) DDR333 DDR266B 6K 75B 133 100 166 133 • • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2, 2.
5 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.
8µs Maximum Average Periodic Refresh Interval 2.
5V (SSTL_2 compatible) I/O VDDQ = 2.
5V ± 0.
2V VDD = 2.
5V ± 0.
2V 6K Speed sort: Supports PC2700/PC2100 modules 75B Speed sort: Supports PC2100 modules Description The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
It is internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations.
An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
The 512Mb DDR SDRAM uses a double-data-rate architecAs with standard SDRAMs, the pipelined, multibank architecture to achieve high-speed operation.
The double data rate ture of DDR SDRAMs allows for concurrent operation, architecture is essentially a 2n prefetch architecture with an DataSheet4U.
com thereby providing high effective bandwidth by hiding row pre- DataShee interface designed to transfer two data words per clock cycle charge and activation time.
at the I/O pins.
A single read or write access for the 512Mb DD...

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