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NT5DS32M16DS

Part Number	NT5DS32M16DS
Manufacturer	Nanya Techology
Description	512Mb DDR SDRAM
Published	Oct 11, 2014
Detailed Description	NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency DDR-333 DDR400 -5T/-5TI DDR500...
Datasheet	NT5DS32M16DS PDF File

Overview

NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Feature CAS Latency Frequency DDR-333 DDR400 -5T/-5TI DDR500 z 2KB page size for all configurations.
Units Speed Sorts -6K/-6KI CL-tRCD-tRP -4T z DQS is edge-aligned with data for reads and is center-aligned with data for WRITEs 2.
5-3-3 266 333 333 3-3-3 266 333 400 3-4-4 333 500 tCK CL=2 Speed CL=2.
5 CL=3 z Differential clock inputs (CK and CK) Mbps z Data mask (DM) for write data z DLL aligns DQ and DQS transition with CK transitions.
z Commands entered on each positive CK edge; data z Power Supply Voltage: VDD=VDDQ=2.
5V 0.
2V (DDR-333) VDD=VDDQ=2.
6V 0.
1V (DDR-400/500) and data mask referenced to both edges of DQS z Burst Lengths: 2, 4 or 8 z Auto Precharge option for each burst access z Auto-Refresh and Self-Refresh Mode z 7.
8 µs max.
Average Periodic Refresh Interval z 2.
5V (SSTL_2 compatible) I/O z RoHS compliance z JEDEC Standard Compliance z Packages: 66 pin TSOPII z z z z 4 internal memory banks for concurrent operation.
CAS Latency: 2, 2.
5 and 3 Double Data Rate Architecture Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
z Industrial grade device support -40℃~95℃ Operating Temperature (-75I/-6KI/5TI) 1 REV 1.
1 Jul.
2011 CONSUMER DRAM NT5DS64M8DS NT5DS32M16DS 512Mb DDR SDRAM Description Nanya 512Mb SDRAMs is a high-speed CMOS Double Data Rate SDRAM containing 536,870,912 bits.
It is internally configured as a qual-bank DRAM.
The 512Mb chip is organized as 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device.
These synchronous devices achieve high speed double-data-rate transfer rates of up to 500 (400, 333 or 266) MHz for general applications.
The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high speed operation.
The double data rate architecture is essentially a 2 prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
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