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NT5DS32M16BG

Part Number	NT5DS32M16BG
Manufacturer	Nanya Techology
Description	(NT5DSxxMxBx) 512Mb DDR SDRAM
Published	Sep 24, 2006
Detailed Description	www.DataSheet4U.com NT5DS128M4BF / NT5DS128M4BT/ NT5DS128M4BG (Green) / NT5DS128M4BS (Green) NT5DS64M8BF / NT5DS64M8BT/...
Datasheet	NT5DS32M16BG PDF File

Overview

www.
DataSheet4U.
com NT5DS128M4BF / NT5DS128M4BT/ NT5DS128M4BG (Green) / NT5DS128M4BS (Green) NT5DS64M8BF / NT5DS64M8BT/ NT5DS64M8BG (Green) / NT5DS64M8BS (Green) NT5DS32M16BF / NT5DS32M16BT / NT5DS32M16BG (Green) / NT5DS32M16BS (Green) 512Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 2 2.
5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2 / 2.
5 (6K & 75B), 2.
5 / 3 (5T) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.
8µs Maximum Average Periodic Refresh Interval 2.
5V (SSTL_2 compatible) I/O VDD = VDDQ = 2.
5V ± 0.
2V (6K & 75B) VDD = VDDQ = 2.
6V ± 0.
1V (5T) Description NT5DS128M4BF, NT5DS128M4BT, NT5DS64M8BF, NT5DS64M8BT, NT5DS32M16BF and NT5DS32M16BT are die B of 512Mb SDRAM devices based using DDR interface.
They are all based on Nanya’s 110 nm design process.
accessed.
The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write The 512Mb DDR SDRAM is a high-speed CMOS, dynamic burst lengths of 2, 4, or 8 locations.
An Auto Precharge funcrandom-access memory containing 536,870,912 bits.
It is tion may be enabled to provide a self-timed row precharge DataSheet4U.
com e internally confi...

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