DatasheetsPDF.com

PLL102-03

Part Number	PLL102-03
Manufacturer	PhaseLink Corporation
Description	Low Skew Output Buffer
Published	Oct 28, 2008
Detailed Description	PLL102-03 Low Skew Output Buffer FEATURES Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spec...
Datasheet	PLL102-03 PDF File

Overview

PLL102-03 Low Skew Output Buffer FEATURES Frequency range 75 ~ 180MHz.
Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
• Zero input - output delay.
• Less than 700 ps device - device skew.
• Less than 250 ps skew between outputs.
www.
DataSheet4U.
com • Less than 150 ps cycle - cycle jitter.
• Output Enable function tri-state outputs.
• 3.
3V operation.
• Available in 8-Pin 150mil SOIC GREEN package.
• • PIN CONFIGURATION REF CLK2 CLK1 GND 1 2 3 4 8 7 6 5 CLKOUT CLK4 VDD CLK3 PLL102-03 Remark If REF clock is stopped for more than 10us after it has already been provided to the chip, and after power-u...

Similar Datasheet

PLL102-03 Low Skew Output Buffer - PhaseLink Corporation
PLL102-04 Low Skew Output Buffer - PhaseLink Corporation
PLL102-05 Low Skew Output Buffer - PhaseLink Corporation
PLL102-10 Low Skew Output Buffer - PhaseLink Corporation
PLL102-108 Programmable DDR Zero Delay Clock Driver - PhaseLink Corporation
PLL102-109 Programmable DDR Zero Delay Clock Driver - PhaseLink Corporation
PLL102-15 Low Skew Output Buffer - PhaseLink Corporation

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)