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PLL102-04

Part Number	PLL102-04
Manufacturer	PhaseLink Corporation
Description	Low Skew Output Buffer
Published	Oct 28, 2008
Detailed Description	PLL102-04 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spec...
Datasheet	PLL102-04 PDF File

Overview

PLL102-04 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz.
Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
• Zero input - output delay.
• Less than 700 ps device - device skew.
• Less than 250 ps skew between outputs.
www.
DataSheet4U.
com • Less than 200 ps cycle - cycle jitter.
• Output Enable function tri-state outputs.
• 3.
3V operation.
• Available in 8-Pin 150mil SOIC.
• • PIN CONFIGURATION REF CLK2 CLK1 GND 1 2 3 4 8 7 6 5 CLKOUT CLK4 VDD CLK3 PLL102-04 DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks ...

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