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ALD

Abracon Corporation
Part Number ALD
Manufacturer Abracon Corporation
Description CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
Published Jan 9, 2010
Detailed Description CERAMIC SMD CRYSTAL CLOCK OSCILLATOR ALD SERIES : PRELIMINARY APPLICATIONS: • SONET, xDSL • SDH, CPE • STB 5.08 x 7.0 x ...
Datasheet PDF File ALD PDF File

ALD
ALD

Overview
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR ALD SERIES : PRELIMINARY APPLICATIONS: • SONET, xDSL • SDH, CPE • STB 5.
08 x 7.
0 x 1.
8mm | | | | | | | | | | | | | | | FEATURES: • Based on a proprietary digital multiplier • 2.
5V to 3.
3V +/- 5% operation • Tri-State Output • Ceramic SMD, low profile package • Low Phase Jitter • 156.
25MHz, 187.
5MHz, and 212.
5MHz applications STANDARD SPECIFICATIONS: PARAMETERS Frequency Range Operating Temperature Storage Temperature Overall Frequency Stability Supply Voltage (Vdd) Linearity Jitter (12KHz - 20MHz) Phase Noise 750 KHz to 800 MHz 0°C to + 70°C (see options) - 40°C to + 85°C ± 50 ppm max.
(see options) 2.
5V to 3.
3 Vdc ± 5% 5% typ, 10% max.
RMS phase jitter 3pS typ.
< 5pS max.
period jitter < 35pS peak to peak -109 dBc/Hz @ 1kHz Offset from 622.
08MHz -110 dBc/Hz @ 10kHz Offset from 622.
08MHz -109 dBc/Hz @ 100kHz Offset from 622.
08MHz “1” (VIH > 0.
7*VDD) or open: Oscillation/ “0” (VIH > 0.
3*VDD) No Oscillation/Hi Z 80mA (Fo < 155.
52MHz), 100mA (Fo < 155.
52MHz) 45% min, 50% typical, 55% max.
VDD -1.
025V min, VDD -0.
880V max.
VDD -1.
810V min, VDD -1.
620V max.
1.
5ns max, 0.
6nSec typical 1.
5ns max, 0.
6nSec typical 1.
6ns max, 1.
2ns typical 45% min, 50% typical, 55% max 60mA max, 55mA typical.
45% min, 50% typical, 55% max 247mV min, 355mV typical, 454mV max -50mV min, 50mV max VOH = 1.
6V max, 1.
4V typical VOL = 0.
9V min, 1.
1V typical VOS = 1.
125V min, 1.
2V typical, 1.
375V max ∆VOS = 0mV min, 3mV typical, 25mV max ±10µA max, ±1µA typical 0.
2ns min, 0.
5ns typical, 0.
7ns max 0.
2ns min, 0.
5ns typical, 0.
7ns max 30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.
abracon.
com Tri-State Function PECL Supply Current (IDD) Symmetry (Duty Cycle) Output Logic High Output Logic Low Clock Rise time (tr) @ 20/80% Clock Fall time (tf) @ 80/20% www.
DataSheet4U.
com CMOS Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load] Output Clock Duty Cycle [Measured @ 50% VDD] LVDS Supply Current (IDD) [Fout = ...


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