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ICS8602

Part Number	ICS8602
Manufacturer	Integrated Circuit Systems
Description	DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Published	May 13, 2010
Detailed Description	PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR FEATURES...
Datasheet	ICS8602 PDF File

Overview

PRELIMINARY Integrated Circuit Systems, Inc.
ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR FEATURES • Fully integrated PLL • 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 15.
625MHz to 250MHz • Input frequency range: 15.
625MHz to 250MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Cycle-to-cycle jitter: 36ps (typical) • Output skew: 125ps (maximum) • Static Phase Offset: TBD±100ps (typical) • 3.
3V supply voltage • 0°C to 70°C ambient operating temperature GENERAL DESCRIPTION The ICS8602 is a high performance, low skew, ,&6 1-to-9 Differential-to-LVCMOS/LVTTL Zero DeHiPerClockS™ lay Buffer and a member of the HiPerClockS™ family of High Performance Clocks Solutions from ICS.
The CLK, nCLK pair can accept most standard differential input levels.
The VCO operates at a frequency range of 250MHz to 500MHz.
The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks.
The device is designed only for 1:1 input/output frequency ratios.
The output divider allows a wide input/output frequency range with the 250MHz to www.
DataSheet4U.
com 500MHz VCO.
The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes.
In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be doubled by utilizing the ability of the outputs to drive two series terminated lines.
The differential reference clock input will accept any differential signal levels.
BLOCK DIAGRAM PIN ASSIGNMENT PLL_SEL VDDO VDDO GND GND Q6 Q8 Q7 Q0 SEL0 SEL1 Q1 32 31 30 29 28 27 26 25 VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FB_IN VDDO Q0 GND Q1 VD...

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