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8T49N281

Integrated Device Technology
Part Number 8T49N281
Manufacturer Integrated Device Technology
Description NG Octal Universal Frequency Translator
Published Mar 8, 2016
Detailed Description FemtoClock® NG Octal Universal Frequency Translator 8T49N281 DATA SHEET General Description The 8T49N281 has a fractio...
Datasheet PDF File 8T49N281 PDF File

8T49N281
8T49N281

Overview
FemtoClock® NG Octal Universal Frequency Translator 8T49N281 DATA SHEET General Description The 8T49N281 has a fractional-feedback PLL that can be used as a jitter attenuator or frequency translator.
It is equipped with six integer and two fractional output dividers, allowing the generation of up to 8 different output frequencies, ranging from 8kHz to 1GHz.
Three of these frequencies are completely independent of each other and the inputs.
The other five are related frequencies.
The eight outputs may select among LVPECL, LVDS or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T G.
709 (2009) FEC rates.
The device may also behave as a frequency synthesizer.
The 8T49N281 accepts up to two differential or single-ended input clocks and a crystal input.
The PLL can lock to either input clock, but both input clocks must be related in frequency.
The device supports hitless reference switching between input clocks.
The device monitors both input clocks for Loss of Signal (LOS).
It generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are supported.
LOS behavior can be set to support gapped or un-gapped clocks.
The 8T49N281 supports holdover with an initial accuracy of ±50ppB from the point where the loss of all applicable input reference(s) has been detected.
It maintains a historical average operating point that may be returned to in holdover at a limited phase slope.
The device places no constraints on input to output frequency conversion, supporting all FEC rates, including the new revision of ITU-T Recommendation G.
709 (2009), most with 0ppm conversion error.
The PLL has a register-selectable loop bandwidth from 0.
5Hz to 512Hz.
Each output supports individual phase delay settings to allow output-output alignment.
The device supports Output Enable inputs and Loc...


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