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8T49N282

Integrated Device Technology
Part Number 8T49N282
Manufacturer Integrated Device Technology
Description NG Octal Universal Frequency Translator
Published Mar 8, 2016
Detailed Description FemtoClock® NG Octal Universal Frequency Translator 8T49N282 DATA SHEET General Description The 8T49N282 has two indep...
Datasheet PDF File 8T49N282 PDF File

8T49N282
8T49N282

Overview
FemtoClock® NG Octal Universal Frequency Translator 8T49N282 DATA SHEET General Description The 8T49N282 has two independent, fractional-feedback PLLs that can be used as jitter attenuators and frequency translators.
It is equipped with six integer and two fractional output dividers, allowing the generation of up to eight different output frequencies, ranging from 8kHz to 1GHz.
Four of these frequencies are completely independent of each other and the inputs.
The other four are related frequencies.
The eight outputs may select among LVPECL, LVDS or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T G.
709 (2009) FEC rates.
The device may also behave as a frequency synthesizer.
The 8T49N282 accepts up to four differential or single-ended input clocks and a crystal input.
Each of the two internal PLLs can lock to different input clocks which may be of independent frequencies.
The other two input clocks are intended for redundant backup of the primary clocks and must be related in frequency to their primary.
The device supports hitless reference switching between input clocks.
The device monitors all input clocks for Loss of Signal (LOS), and generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are supported.
LOS behavior can be set to support gapped or un-gapped clocks.
The 8T49N282 supports holdover for each PLL.
The holdover has an initial accuracy of ±50ppB from the point where the loss of all applicable input reference(s) has been detected.
It maintains a historical average operating point for each PLL that may be returned to in holdover at a limited phase slope.
The device places no constraints on input to output frequency conversion, supporting all FEC rates, including the new revision of ITU-T Recommendation G.
709 (2009), most with 0ppm conversion erro...


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