MOSFET. FDMS3664S Datasheet

FDMS3664S Datasheet PDF, Equivalent


Part Number

FDMS3664S

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 16 Pages
PDF Download
Download FDMS3664S Datasheet PDF


FDMS3664S Datasheet
FDMS3664S
PowerTrench® Power Stage
January 2015
Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A
„ Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A
Q2: N-Channel
„ Max rDS(on) = 2.6 mΩ at VGS = 10 V, ID = 25 A
„ Max rDS(on) = 3.2 mΩ at VGS = 4.5 V, ID = 22 A
„ Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
„ MOSFET integration enables optimum layout for
lower circuit inductance and reduced switch node
ringing
„ RoHS Compliant
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
Pin 1
Pin 1
G1
D1
D1
D1
D1
S2 5
Q2
4 D1
PHASE
(S1/D2)
G2
S2
S2
S2
Top Power 56 Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
S2 6
S2 7
G2 8
PHASE
3 D1
2 D1
Q1 1 G1
Symbol
VDS
VDSt
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Drain to Source Transient Voltage ( tTransient < 100 ns)
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
33 33
±20 ±12
30 60
60
131a
118
251b
40
334
2.21a
11c
100
485
2.51b
11d
-55 to +150
Units
V
V
V
A
mJ
W
°C
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
571a
1251c
2.9
501b
1201d
2.3
°C/W
Device Marking
22CF
10OD
Device
FDMS3664S
Package
Power 56
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2012 Fairchild Semiconductor Corporation
FDMS3664S Rev.C5
1
www.fairchildsemi.com

FDMS3664S Datasheet
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1 30
Q2 30
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
Q1
Q2
Gate to Source Leakage Current
VGS = 20 V, VDS= 0 V
VGS = 12 V, VDS= 0 V
Q1
Q2
V
16
18
mV/°C
1 μA
500 μA
100 nA
100 nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1 1.1 1.9
Q2 1.1 1.6
2.7
2.2
V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-3
mV/°C
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 11 A
VGS = 10 V, ID = 13 A , TJ = 125 °C
VGS = 10 V, ID = 25 A
VGS = 4.5 V, ID = 22 A
VGS = 10 V, ID = 25 A , TJ = 125 °C
Q1
Q2
48
6 11
5.7 8.7
mΩ
2.0 2.6
2.5 3.2
2.9 4.5
VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 25 A
Q1 62
Q2 179
S
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
1325
2515
466
645
46
74
1765
3345
620
860
70
115
pF
pF
pF
Q1 0.2 0.6
Q2 0.2 0.9
2
3
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg Total Gate Charge
Qg Total Gate Charge
Qgs Gate to Source Gate Charge
Qgd Gate to Drain “Miller” Charge
Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 25 A, RGEN = 6 Ω
VGS = 0 V to 10 V Q1:
VDD = 15 V,
VGS = 0 V to 4.5 V ID = 13 A
Q2:
VDD = 15 V,
ID = 25 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
7.7
9.2
15
18
ns
2.2
3.4
10
10
ns
19
28
34
46
ns
1.8
2.4
10
10
ns
21
37
29
52
nC
9.5
17
13
24
nC
3.9
5.9
nC
2.6
4
nC
©2012 Fairchild Semiconductor Corporation
FDMS3664S Rev.C5
2
www.fairchildsemi.com


Features Datasheet pdf FDMS3664S PowerTrench® Power Stage FDM S3664S PowerTrench® Power Stage Janua ry 2015 Asymmetric Dual N-Channel MOSF ET Features General Description Q1: N-Channel „ Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A „ Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A Q2: N-Cha nnel „ Max rDS(on) = 2.6 mΩ at VGS = 10 V, ID = 25 A „ Max rDS(on) = 3.2 m at VGS = 4.5 V, ID = 22 A „ Low indu ctance packaging shortens rise/fall tim es, resulting in lower switching losses „ MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing „ RoHS Co mpliant This device includes two speci alized N-Channel MOSFETs in a dual PQFN package. The switch node has been inte rnally connected to enable easy placeme nt and routing of synchronous buck conv erters. The control MOSFET (Q1) and syn chronous SyncFETTM (Q2) have been desig ned to provide optimal power efficiency . Applications „ Computing „ Communic ations „ General Purpose Point of Load „ Notebook VCORE Pin .
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