VCXO PLL. MK2049-34 Datasheet

MK2049-34 PLL. Datasheet pdf. Equivalent

Part MK2049-34
Description CLOCK VCXO PLL
Feature 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL DATASHEET MK2049-34 Description The MK2049-34 is a VCXO Pha.
Manufacture Renesas
Datasheet
Download MK2049-34 Datasheet



MK2049-34
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
DATASHEET
MK2049-34
Description
The MK2049-34 is a VCXO Phased Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a reference, the
MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and
other communications frequencies. This allows for the
generation of clocks frequency-locked and phase-locked to
an 8 kHz backplane clock, simplifying clock synchronization
in communications systems. The MK2409-34 can also
accept a T1 or E1 input clock and provide the same output
for loop timing. All outputs are frequency locked together
and to the input.
This part also has a jitter-attenuated Buffer capability. In this
mode, the MK2049-34 is ideal for filtering jitter from 27 MHz
video clocks or other clocks with high jitter.
ICS can customize these devices for many other different
frequencies.
Features
Packaged in 20-pin SOIC
3.3 V + 5% operation
Fixed I/O phase relationship on all selections
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, Loop
Timing frequencies, or 10 to 36 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 to 36 MHz
input and x1/x0.5 or x2/x4 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3, ISDN, xDSL,
and the OC3 submultiples
See also the MK2049-36 and MK2049-45
Block Diagram
INPUT REFERENCE
CLOCK
(TYPICALLY 8KHZ)
4
FREQUENCY SELECT
EXTERNAL PULLABLE CRYSTAL
(external loop filter)
VCXO-BASED
PLL
(MASTER CLOCK
GENERATOR)
FREQUENCY
MULTIPLYING
PLL
2
CLOCK OUTPUT
CLOCK OUTPUT / 2
8 KHZ (REGENERATED)
IDT® 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
1
MK2049-34 REV F 102203



MK2049-34
MK2049-34
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
VCXO AND SYNTHESIZER
Pin Assignment
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
1
2
3
4
5
6
7
8
9
10
20 FS0
19 RES
18 CAP2
17 GND
16 CAP1
15 VDD
14 GND
13 ICLK
12 FS3
11 FS2
20-pin (300) mil SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RES
FS0
Pin
Type
Input
XO
XI
Power
-
Power
Power
Output
Output
Output
Input
Input
Input
Power
Power
Loop
Filter
Power
Loop
-
Input
Pin Description
Frequency select 1. Determines CLK input/outputs per table on page 3.
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
Power supply. Connect to +3.3 V.
Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
Power supply. Connect to +3.3 V.
Connect to ground
Clock output determined by status of FS3:0 per tables on page 3.
Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of
CLK.
Recovered 8 kHz clock output.
Frequency select 2. Determines CLK input/outputs per tables on page 3.
Frequency select 3. Determines CLK input/outputs per tables on page 3.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Power Supply. Connect to +3.3 V.
Connect the loop filter ceramic capacitors and resistor between this pin and
CAP2.
Connect to ground.
Connect the loop filter ceramic capacitors and resistor between this pin and
Connect a 10-200kΩ resistor to ground. Contact ICS at telecom@icst.com for
recommended value for your application.
Frequency select 0. Determines CLK input/outputs per table on page 3.
IDT® 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
2
MK2049-34 REV F 102203





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