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PLL102-15

Part Number	PLL102-15
Manufacturer	PhaseLink Corporation
Description	Low Skew Output Buffer
Published	Oct 28, 2008
Detailed Description	PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec ...
Datasheet	PLL102-15 PDF File

Overview

PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz.
Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).
• Zero input - output delay.
• Less than 700 ps device - device skew.
• Less than 250 ps skew between outputs.
www.
DataSheet4U.
com • Less than 200 ps cycle - cycle jitter.
• Output Enable function tri -state outputs.
• 3.
3V operation.
• Available in 8 -Pin 150mil SOIC.
• • PIN CONFIGURATION VDD CLK1 CLKOUT GND 1 2 3 4 8 7 6 5 N/C CLK3 CLK2 REF_IN PLL102-15 Remark If REF_IN clock is stopped for more than 10us after it has already been provided to the chip, and after power-up, the o...

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