Clock Generator/Synchronizer. AD9548 Datasheet

AD9548 Generator/Synchronizer. Datasheet pdf. Equivalent

Part AD9548
Description Quad/Octal Input Network Clock Generator/Synchronizer
Feature Data Sheet Quad/Octal Input Network Clock Generator/Synchronizer AD9548 FEATURES APPLICATIONS Su.
Manufacture Analog Devices
Datasheet
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AD9548
Data Sheet
Quad/Octal Input Network Clock
Generator/Synchronizer
AD9548
FEATURES
APPLICATIONS
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Auto/manual holdover and reference switchover
4 pairs of reference input pins with each pair configurable as
a single differential input or as 2 independent single-
ended inputs
Input reference frequencies from 1 Hz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a
single differential LVDS/LVPECL output or as 2 single-
ended CMOS outputs
Output frequencies up to 450 MHz
30-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
88-lead LFCSP package
Network synchronization
Cleanup of reference clock jitter
GPS 1 pulse per second synchronization
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3 reference clocks
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9548 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9548 generates an output clock synchronized to one of up to
four differential or eight single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The AD9548
continuously generates a clean (low jitter), valid output clock
even when all references have failed by means of a digitally
controlled loop and holdover circuitry.
The AD9548 operates over an industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
STABLE
SOURCE
ANALOG
FILTER
CLOCK
MULTIPLIER
REFERENCE INPUTS
AND
MONITOR MUX
AD9548
DIGITAL
PLL
DAC
SYNC
CLOCK DISTRIBUTION
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
CHANNEL 2
DIVIDER
CHANNEL 3
DIVIDER
SERIAL CONTROL INTERFACE
(SPI or I2C)
EEPROM
STATUS AND
CONTROL PINS
Figure 1.
Rev. G
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AD9548
AD9548* Product Page Quick Links
Last Content Update: 08/30/2016
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Evaluation Kits
• AD9548 Evaluation Board
• FPGA Mezzanine Card for Wireless Communications
Documentation
Application Notes
• AN-1002: The AD9548 as a GPS Disciplined Stratum 2
Clock
• AN-1061: Behavior of the AD9548 Phase and Frequency
Lock Detectors in the Presence of Random Jitter
• AN-1064: Understanding the Input Reference Monitors of
the AD9548
• AN-1079: Determining the Maximum Tolerable Frequency
Drift Rate of the AD9548 System Clock in Low Loop
Bandwidth Applications
Data Sheet
• AD9548: Quad/Octal Input Network Clock Generator/
Synchronizer Data Sheet
User Guides
• UG-639: Evaluating the AD9547 and AD9548 Digital PLL
Clock Synthesizers
Tools and Simulations
• AD9548 IBIS Models
Reference Materials
Product Selection Guide
• RF Source Booklet
Technical Articles
• Synchronizing NxN MIMO Basestations to an External
Timing Reference
Design Resources
• AD9548 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
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