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74ALVCH16646

NXP
Part Number 74ALVCH16646
Manufacturer NXP
Description 16-bit bus transceiver/register
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74ALVCH16646 16-bit bus transceiver/register (3-State) Product specification IC24 Data Handbook 199...
Datasheet PDF File 74ALVCH16646 PDF File

74ALVCH16646
74ALVCH16646

Overview
INTEGRATED CIRCUITS 74ALVCH16646 16-bit bus transceiver/register (3-State) Product specification IC24 Data Handbook 1998 Sep 03 Philips Semiconductors Philips Semiconductors Product specification 16-bit bus transceiver/register (3-State) 74ALVCH16646 FEATURES • Complies with JEDEC standard no.
8-1A • CMOS low power consumption • MULTIBYTETM flow-through pin-out architecture • Low inductance, multiple VCC and ground pins for minimum noise and ground bounce minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
PIN CONFIGURATION 1DIR 1 1CPAB 2 1SAB 3 GND 4 1A0 5 1A1 6 VCC 7 1A2 8 1A3 9 56 1OE 55 1CPBA 54 1SBA 53 GND 52 1B0 51 1B1 50 VCC 49 1B2 48 1B3 47 1B4 46 GND 45 1B5 44 1B6 43 1B7 42 2B0 41 2B1 40 2B2 39 GND 38 2B3 37 2B4 36 2B5 35 VCC 34 2B6 33 2B7 32 GND 31 2SBA 30 2CPBA 29 2OE • Direct interface with TTL levels • Current drive ± 24 mA at 3.
0 V • Output drive capability 50Ω transmission lines @ 85°C • All inputs have bushold circuitry DESCRIPTION The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers.
Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level.
Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function.
In the transceiver mode, data present at the high-impedance port may be stored in either the ‘A’ or ‘B’ register, or in both.
The select source inputs (SAB and SBA) can multiplex stored and real-time (transparent mode) data.
The direction (DIR) input determines which bus will receive data when OE is active (LOW).
In the isolation mode (OE = HIGH), ‘A’ data may be stored in the ‘B’ register and/or ‘B’ data may be s...


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