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PI6LC4830

Part Number	PI6LC4830
Manufacturer	Pericom Semiconductor
Description	Network Clock Generator
Published	May 13, 2016
Detailed Description	PI6LC4830 HiFlexTM Network Clock Generator Features ÎÎ3.3V supply voltage ÎÎ3 HCSL and 1 LVCMOS 100MHz outputs with OE/...
Datasheet	PI6LC4830 PDF File

Overview

PI6LC4830 HiFlexTM Network Clock Generator Features ÎÎ3.
3V supply voltage ÎÎ3 HCSL and 1 LVCMOS 100MHz outputs with OE/ function ÎÎ1 LVCMOS 100/50MHz selectable ÎÎ25MHz crystal or differential input ÎÎLow 1ps RMS max integrated phase noise design ÎÎPLL Bypass mode for test ÎÎ32 lead 5x5mm TQFN package Description The PI6LC4830 is an LC VCO based low phase noise design intended for the most demanding PCIe® 2.
0 applications.
Use of the ultra-low noise LC VCO allows for much greater noise margins than traditional solutions.
This is ideal for noisy environments.
Pin Configuration VDDA_PLL VDD QA_OE VDD_Out IREF QA0+ QA0GND PLL_Byps REF_OUT_OE QB_OE QB_DIV2 VDD_PLL IN+ INVDD_REF_Out 32 31 30 29 28 1 27 26 25 24 2 23 3 22 4 GND 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 QA1+ QA1VDD_Out QA2+ QA2GND QA_CMOS VDD_OutA_SE REF_OUT+ REF_OUT- IN_SEL X1 X2 VDD_OSC VDD_OutB_SE QB_CMOS Block Diagram IN_SEL OSC IN+ IN- 12-0238 PLL_Byps REF_OUT_OE REF_OUT PLL /R QA0:QA2 100MHz HCSL Outputs QA_CMOS QA_OE QB_CMOS /2 QB_DIV2 QB_OE 1 PI6LC4830 Rev B 08/17/12 Pin Description Pin Number Pin Name 20, 21, 23, 24, QA0+, QA0-, QA1+, 26, 27 QA1-, QA2+, QA2- Type Output (HCSL) 9, 10 REF_Out+, REF_Out- Output (LVPECL) 12 X1 13 X2 6, 7 IN+, IN- Input Output Input (Differential) 11 IN_SEL Input (LVCMOS) 1 PLL_Byps Input (LVCMOS) 30, 3 14 5 22, 29 32 19, 25 18 16 17 15 4 28 8 2 31 QA_OE, QB_OE VDD_OSC VDD_PLL VDD_Out VDDA_PLL GND QA_CMOS QB_CMOS VDD_OutA_SE VDD_OutB_SE QB_DIV2 IREF VDD_REF_OUT REF_OUT_OE VDD Input (LVCMOS) Power Power Power Power Power Output (LVCMOS) Output (LVCMOS) Power Power Input (LVCMOS) Output Power Input (LVCMOS) Power PI6LC4830 HiFlexTM Network Clock Generator Description 100MHz HCSL Outputs 25MHz LVPECL output from fundamental oscillator core Crystal input pin Oscillator output pin HCSL/LVPECL/LVDS inputs Low selects X1 and X2, High selects In+, In-.
Internal pull up is 100k Ohms If Low, output buffers are switched to the PL...

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