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BST122

NXP
Part Number BST122
Manufacturer NXP
Description P-channel transistor
Published Mar 23, 2005
Detailed Description DISCRETE SEMICONDUCTORS DATA SHEET BST122 P-channel enhancement mode vertical D-MOS transistor Product specification Fi...
Datasheet PDF File BST122 PDF File

BST122
BST122

Overview
DISCRETE SEMICONDUCTORS DATA SHEET BST122 P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor DESCRIPTION P-channel vertical D-MOS transistor in SOT89 envelope and intended for use in relay, high-speed and line-transformer drivers, using SMD-technology.
FEATURES • Very low RDS(on) • Direct interface to C-MOS, TTL • High-speed switching • No second breakdown QUICK REFERENCE DATA Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance −ID = 200 mA; −VGS = 10 V Transfer admittance −ID = 200 mA; −VDS = 15 V PINNING - SOT89 1 2 3 = source = drain = gate  Yfs typ.
RDS(on) −VDS ±VGSO −ID Ptot BST122 max.
max.
max.
max.
max.
typ.
60 V 20 V 0,25 A 1 W 10 Ω 7.
5 Ω 125 mS PIN CONFIGURATION handbook, halfpage d g 1 Bottom view 2 3 MAM354 s Marking: LN Fig.
1 Simplified outline and symbol.
April 1995 2 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 °C Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note 1.
Transistor mounted on a ceramic substrate: area = 2,5 cm2; thickness = 0,7 mm.
Rth j-a = 125 −VDS ±VGSO −ID −IDM Ptot Tstg Tj max.
max.
max.
max.
max.
max.
60 V 20 V 0.
25 A 0.
5 A 1 W 150 °C BST122 −65 to + 150 °C K/W April 1995 3 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor CHARACTERISTICS Tj = 25 °C unless otherwise specified Drain-source breakdown voltage −ID = 10 µA; VGS = 0 Drain-source leakage current −VDS = 48 V; VGS = 0 Gate-s...


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