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74LV00D

nexperia
Part Number 74LV00D
Manufacturer nexperia
Description Quad 2-input NAND gate
Published Dec 27, 2020
Detailed Description 74LV00 Quad 2-input NAND gate Rev. 5 — 10 September 2021 Product data sheet 1. General description The 74LV00 is a qua...
Datasheet PDF File 74LV00D PDF File

74LV00D
74LV00D

Overview
74LV00 Quad 2-input NAND gate Rev.
5 — 10 September 2021 Product data sheet 1.
General description The 74LV00 is a quad 2-input NAND gate.
Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
2.
Features and benefits • Wide supply voltage range from 1.
0 to 5.
5 V • CMOS low power dissipation • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Optimized for low voltage applications: 1.
0 V to 3.
6 V • Accepts TTL input levels between VCC = 2.
7 V and VCC = 3.
6 V • Typical output ground bounce < 0.
8 V at VCC = 3.
3 V and Tamb = 25 °C • Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.
3 V and Tamb = 25 °C • Complies with JEDEC standards: • JESD8-7 (1.
65 V to 1.
95 V) • JESD8-5 (2.
3 V to 2.
7 V) • JESD8C (2.
7 V to 3.
6 V) • JESD36 (4.
5 V to 5.
5 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range 74LV00D -40 °C to +125 °C 74LV00PW -40 °C to +125 °C 74LV00BQ -40 °C to +125 °C Name Description SO14 plastic small outline package; 14 leads; body width 3.
9 mm TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
4 mm DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5 × 3 × 0.
85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4.
Functional diagram 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 2Y 6 3Y 8 4Y 11 mna212 Fig.
1.
Logic symbol 1 2 & 3 4 5 & 6 9 10 & 8 12 13 & 11 mna246 Fig.
2.
IEC logic symbol 5.
Pinning information 74LV00 Quad 2-input NAND gate A Y B mna211 Fig.
3.
Logic diagram (one gate) 5.
1.
Pinning 74LV00 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y aaa-033972 Fig.
4.
Pin configura...


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