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74LV00BQ

nexperia
Part Number 74LV00BQ
Manufacturer nexperia
Description Quad 2-input NAND gate
Published Dec 27, 2020
Detailed Description 74LV00 Quad 2-input NAND gate Rev. 4 — 9 December 2015 Product data sheet 1. General description The 74LV00 is a low-...
Datasheet PDF File 74LV00BQ PDF File

74LV00BQ
74LV00BQ

Overview
74LV00 Quad 2-input NAND gate Rev.
4 — 9 December 2015 Product data sheet 1.
General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00.
The 74LV00 provides a quad 2-input NAND function.
2.
Features and benefits  Wide operating voltage: 1.
0 V to 5.
5 V  Optimized for low voltage applications: 1.
0 V to 3.
6 V  Accepts TTL input levels between VCC = 2.
7 V and VCC = 3.
6 V  Typical output ground bounce < 0.
8 V at VCC = 3.
3 V and Tamb = 25 C  Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.
3 V and Tamb = 25 C  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74LV00D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.
9 mm 74LV00DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.
3 mm 74LV00PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
4 mm 74LV00BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5  3  0.
85 mm Version SOT108-1 SOT337-1 SOT402-1 SOT762-1 Nexperia 4.
Functional diagram 74LV00 Quad 2-input NAND gate  $  %  $  %  $  %  $  % <  <  <  <  PQD Fig 1.
Logic symbol             PQD Fig 2.
IEC logic symbol 5.
Pinning information 5.
1 Pinning $ < % PQD Fig 3.
Logic diagram (one gate) $  %  <  $  %  <  *1'   9&&  %  $   <  %  $  < DDF Fig 4.
Pin configuration SO14 and (T)SSOP14 WHUPLQDO LQGH[DUHD %  <  $  %  <  /9  $  9&& 9&&   %  $  <  %  $ *1'  <  DDK 7UDQVSDUHQWWRS...


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