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74LV02D

nexperia
Part Number 74LV02D
Manufacturer nexperia
Description Quad 2-input NOR gate
Published Dec 27, 2020
Detailed Description 74LV02 Quad 2-input NOR gate Rev. 04 — 20 December 2007 Product data sheet 1. General description The 74LV02 is a low-...
Datasheet PDF File 74LV02D PDF File

74LV02D
74LV02D


Overview
74LV02 Quad 2-input NOR gate Rev.
04 — 20 December 2007 Product data sheet 1.
General description The 74LV02 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC02 and 74HCT02.
The 74LV02 provides a quad 2-input NOR function.
2.
Features s Wide operating voltage: 1.
0 V to 5.
5 V s Optimized for low voltage applications: 1.
0 V to 3.
6 V s Accepts TTL input levels between VCC = 2.
7 V and VCC = 3.
6 V s Typical output ground bounce < 0.
8 V at VCC = 3.
3 V and Tamb = 25 °C s Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.
3 V and Tamb = 25 °C s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Multiple package options s Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74LV02D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.
9 mm 74LV02PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
4 mm 74LV02BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5 × 3 × 0.
85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4.
Functional diagram 74LV02 Quad 2-input NOR gate 2 1A 3 1B 5 2A 6 2B 8 3A 9 3B 11 4A 12 4B 1Y 1 2Y 4 3Y 10 4Y 13 mna216 Fig 1.
Logic symbol 2 ≥1 3 1 5 ≥1 6 4 8 ≥1 9 10 11 ≥1 12 13 001aah084 Fig 2.
IEC logic symbol 5.
Pinning information 5.
1 Pinning A Y B mna215 Fig 3.
Logic diagram for one gate 1Y 1 1A 2 1B 3 2Y 4 2A 5 2B 6 GND 7 14 VCC 13 4Y 12 4B 02 11 4A 10 3Y 9 3B 8 3A 001aac919 Fig 4.
Pin configuration SO14 and TSSOP14 terminal 1 index area 1A 2 1B 3 2Y 4 2A 5 2B 6 74LV02 1 1Y 14 VCC VCC(1) 13 4Y 12 4B 11 4A 10 3Y 9 3B GND 7 3A 8 001aah093 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material.
It can not be u...


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