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K4S561632D

Part Number	K4S561632D
Manufacturer	Samsung semiconductor
Description	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL
Published	Apr 7, 2005
Detailed Description	www.DataSheet4U.com K4S561632D CMOS SDRAM 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL DataSheet4U.com ...
Datasheet	K4S561632D PDF File

Overview

www.
DataSheet4U.
com K4S561632D CMOS SDRAM 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL DataSheet4U.
com DataShee Revision 0.
1 Aug.
2002 * Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
1 Aug.
2002 DataSheet4U.
com DataSheet4U.
com www.
DataSheet4U.
com K4S561632D Revision History Revision 0.
0 (Jan.
, 2002) -First generation CMOS SDRAM Revision 0.
1(Aug.
,2002) - ICC6 of Low power is changed from 1.
0 to 1.
5 due to typo.
et4U.
com DataSheet4U.
com DataShee Rev.
0.
1 Aug.
2002 DataSheet4U.
com DataSheet4U.
com www.
DataSheet4U.
com K4S561632D 4M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.
3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (8K Cycle) Part No.
K4S561632D-TC/L60 K4S561632D-TC/L7C K4S561632D-TC/L75 K4S561632D-TC/L1H K4S561632D-TC/L1L CMOS SDRAM GENERAL DESCRIPTION The K4S561632D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION Max Freq.
166MHz(CL=3) 133MHz(CL=2) 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54pin TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM I/O Control LWE et4U.
com Bank Select DataSheet4U.
com Data Input Register DataShee LDQM 4M x 16 4M x 16...

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