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MCM6343

Motorola
Part Number MCM6343
Manufacturer Motorola
Description 256K x 15 Bit 3.3 V Asynchronous Fast Static RAM
Published Apr 30, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6343/D Product Preview MCM6343 256K x 16 Bit 3.3 V ...
Datasheet PDF File MCM6343 PDF File

MCM6343
MCM6343

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6343/D Product Preview MCM6343 256K x 16 Bit 3.
3 V Asynchronous Fast Static RAM The MCM6343 is a 4,194,304–bit static random access memory organized as 262,144 words of 16 bits.
Static design eliminates the need for external clocks or timing strobes.
The MCM6343 is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems.
Separate byte enable controls (LB and UB) allow individual bytes to be written and read.
LB controls the lower bits DQ0 to DQ7, while UB controls the upper bits DQ8 to DQ15.
The MCM6343 is available in a 400 mil, 44–lead small–outline SOJ package and a 44–lead TSOP Type II package.
• • • • • • • • Single 3.
3 V ± 0.
3 V Power Supply Fast Access Time: 12/15 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Data Byte Control Fully Static Operation Power Operation: 250/240/230 mA Maximum, Active AC Commercial and Standard Industrial Temperature Option: – 40 to + 85°C BLOCK DIAGRAM G OUTPUT ENABLE BUFFER 9 A 18 ADDRESS BUFFERS 9 ROW COLUMN DECODER DECODER 8 HIGH BYTE OUTPUT ENABLE LOW BYTE OUTPUT ENABLE 8 HIGH BYTE OUTPUT BUFFER HIGH BYTE WRITE DRIVER 8 YJ PACKAGE 400 MIL SOJ CASE 919–01 TS PACKAGE TSOP TYPE II CASE 924A–02 PIN ASSIGNMENT A A A A A E DQ0 DQ1 DQ2 DQ3 VDD VSS DQ4 DQ5 DQ6 DQ7 W A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A A A G UB LB DQ15 DQ14 DQ13 DQ12 VSS VDD DQ11 DQ10 DQ9 DQ8 NC A A A A A E CHIP ENABLE BUFFER 256K x 16 BIT MEMORY ARRAY 16 SENSE AMPS 8 8 W WRITE ENABLE BUFFER LOW BYTE OUTPUT BUFFER 8 LOW BYTE WRITE DRIVER 8 A PIN NAMES 8 A0 – A17 .
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Address Input E .
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Chip Enable W .
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Write Enable G .
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