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HEF4041B

NXP
Part Number HEF4041B
Manufacturer NXP
Description Quadruple true/complement buffer
Published Mar 23, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family ...
Datasheet PDF File HEF4041B PDF File

HEF4041B
HEF4041B

Overview
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4041B buffers Quadruple true/complement buffer Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple true/complement buffer DESCRIPTION The HEF4041B is a quadruple true/complement buffer which provides both an inverted active LOW output (O) and a non-inverted active HIGH output (O) for each input (I).
The buffers exhibit high current output capability suitable for driving TTL or high capacitive loads.
HEF4041B buffers Fig.
2 Pinning diagram.
HEF4041BP(N): HEF4041BD(F): HEF4041BT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.
3 Logic diagram (one buffer).
APPLICATION INFORMATION Some examples of applications for the HEF4041B are: • LOCMOS to DTL/TTL converter • High current sink and source driver Fig.
1 Functional diagram.
FAMILY DATA, IDD LIMITS category BUFFERS See Family Specifications January 1995 2 Philips Semiconductors Product specification Quadruple true/complement buffer DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD Tamb (°C) VDD V Output (source) current HIGH HIGH Output (sink) current LOW 5 10 15 5 4,75 10 15 VOH V 4,6 9,5 13,5 2,5 0,4 0,5 1,5 IOL −IOH −IOH VOL V SYMBOL −40 +25 HEF4041B buffers +85 MIN.
1,0 2,7 10,0 3,0 1,35 4,5 15,0 MAX.
mA mA mA mA mA mA mA MIN.
MAX.
MIN.
TYP.
1,6 4,5 16,0 5,0 2,0 7,5 23,0 1,3 3,6 14,0 4,0 1,7 6,0 20,0 2,6 7,0 30,0 8,0 4,0 12,0 35,0 AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH In → On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times On → On HIGH to LOW LOW to HIGH 10 15 5 10 15 5 10 15 tTLH tTHL tPLH tP...


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