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BSP205

NXP
Part Number BSP205
Manufacturer NXP
Description P-channel enhancement mode vertical D-MOS transistor
Published Mar 23, 2005
Detailed Description DISCRETE SEMICONDUCTORS DATA SHEET BSP205 P-channel enhancement mode vertical D-MOS transistor Product specification Fi...
Datasheet PDF File BSP205 PDF File

BSP205
BSP205

Overview
DISCRETE SEMICONDUCTORS DATA SHEET BSP205 P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor DESCRIPTION P-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and intended for use in relay, high-speed and line-transformer drivers.
FEATURES • Very low RDS(on) • Direct interface to C-MOS, TTL, etc.
• High-speed switching • No secondary breakdown PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain PIN CONFIGURATION Marking code BSP205 QUICK REFERENCE DATA Drain-source voltage Drain current (DC) Drain-source ON-resistance −ID = 200 mA; −VGS = 10 V Gate threshold voltage RDS(on) −VGS(th) max.
max.
−VDS −ID max.
max.
BSP205 60 V 275 mA 10 Ω 3.
5 V handbook, halfpage 4 d g 1 Top view 2 3 MAM121 s Fig.
1 Simplified outline and symbol.
April 1995 2 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 °C (note 1) Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note Rth j-a = −VDS ±VGSO −ID −IDM Ptot Tstg Tj max.
max.
max.
max.
max.
max.
BSP205 60 V 20 V 275 mA 550 mA 1.
5 W 150 °C −65 to 150 °C 83.
3 K/W 1.
Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.
5 mm; mounting pad for the drain lead min.
6 cm2.
April 1995 3 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor CHARACTERISTICS Tj = 25 °C unless otherwise specified Drain-source breakdown voltage −ID = 10 µA; VGS = 0 Drain-source leakage current −VDS = 48 V; VGS = 0 Gate-source leakage current ± VGS = 20 V; VDS = 0 Gate thresho...


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