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74AVC16834A

nexperia
Part Number 74AVC16834A
Manufacturer nexperia
Description 18-bit registered driver
Published Jul 23, 2019
Detailed Description 74AVC16834A 18-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state Rev. 6 — 1...
Datasheet PDF File 74AVC16834A PDF File

74AVC16834A
74AVC16834A


Overview
74AVC16834A 18-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state Rev.
6 — 12 September 2018 Product data sheet 1.
General description The 74AVC16834A is an 18-bit universal bus driver.
Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).
This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.
See Fig.
5 for typical curves.
2.
Features and benefits • Wide supply voltage range from 1.
2 V to 3.
6 V • Complies with JEDEC standards: • JESD8-7 (1.
2 V to 1.
95 V) • JESD8-5 (1.
8 V to 2.
7 V) • JESD8-1A (2.
7 V to 3.
6 V) • CMOS low power consumption • Input/output tolerant up to 3.
6 V • Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation • Low inductance multiple VCC and GND pins to minimize noise and ground bounce • Power off disables 74AVC16834A outputs, permitting Live Insertion • Integrated input diodes to minimize input overshoot and undershoot 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74AVC16834ADGG -40 °C to + 85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.
1 mm Version SOT364-1 Nexperia 74AVC16834A 18-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state 4.
Functional diagram OE CP LE A1 D LE Y1 CP Fig.
1.
to the 17 other channels Logic diagram VCC aaa-027713 A1 002aac725 Fig.
3.
Typical input (data or control) OE CP LE 27 30 28 EN1 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1 ...


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