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74AVC16835

NXP
Part Number 74AVC16835
Manufacturer NXP
Description 18-bit registered driver
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74AVC16835 18-bit registered driver (3-State) Preliminary specification Replaces datasheet 74AVC168...
Datasheet PDF File 74AVC16835 PDF File

74AVC16835
74AVC16835

Overview
INTEGRATED CIRCUITS 74AVC16835 18-bit registered driver (3-State) Preliminary specification Replaces datasheet 74AVC16835/74AVCH16835 dated 1998 Dec 07 1999 Jul 23 Philips Semiconductors Philips Semiconductors Preliminary specification 18-bit Registered Driver (3-State) 74AVC16835 FEATURES • Wide supply voltage range of 1.
2 V to 3.
6 V • Complies with JEDEC standard no.
8-1A/5/7.
• CMOS low power consumption • Input/output tolerant up to 3.
6 V • DCO (Dynamic Controlled Output) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation PIN CONFIGURATION NC NC Y0 GND Y1 Y2 VCC Y3 Y4 Y5 GND Y6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND NC A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 CP GND • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • Power off disables 74AVC16835 outputs, permitting Live Insertion DESCRIPTION The 74AVC16835 is a 18-bit universal bus driver.
Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).
This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.
See the graphs on page 8 for typical curves.
Y7 Y8 Y9 Y10 Y11 GND Y12 Y13 Y14 VCC Y15 Y16 GND Y17 OE LE SH00130 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.
0 ns; CL = 30 pF.
PARAMETER SYMBOL tPHL/tPLH Propagation delay An to Yn Propagation delay LE to Yn; CP to Yn Input capacitance Power dissipation dissi ation capacitance ca acitance per er buffer VI = GND to VCC1 Outputs enabled Output disabled VCC = 1.
8 V VCC = 2.
5...


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