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74AVC16835A

nexperia
Part Number 74AVC16835A
Manufacturer nexperia
Description 18-bit registered driver
Published Jul 23, 2019
Detailed Description 74AVC16835A 18-bit registered driver with Dynamic Controlled Outputs; 3-state Rev. 6 — 24 September 2018 Product dat...
Datasheet PDF File 74AVC16835A PDF File

74AVC16835A
74AVC16835A

Overview
74AVC16835A 18-bit registered driver with Dynamic Controlled Outputs; 3-state Rev.
6 — 24 September 2018 Product data sheet 1.
General description The 74AVC16835A is an 18-bit universal bus driver.
Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).
This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.
See Fig.
5 for typical curves.
2.
Features and benefits • Wide supply voltage range from 1.
2 V to 3.
6 V • Complies with JEDEC standards: • JESD8-7 (1.
2 V to 1.
95 V) • JESD8-5 (1.
8 V to 2.
7 V) • JESD8-1A (2.
7 V to 3.
6 V) • CMOS low power consumption • Input/output tolerant up to 3.
6 V • Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation • Low inductance multiple VCC and GND pins to minimize noise and ground bounce • Power off disables 74AVC16835A outputs, permitting Live Insertion • Integrated input diodes to minimize input overshoot and undershoot 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74AVC16835ADGG -40 °C to + 85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.
1 mm Version SOT364-1 Nexperia 74AVC16835A 18-bit registered driver with Dynamic Controlled Outputs; 3-state 4.
Functional diagram OE CP LE A1 D LE CP Y1 to the 17 other channels aaa-027574 Fig.
1.
Logic diagram VCC A1 002aac725 Fig.
3.
Typical input (data or control) OE 27 CP 30 LE 28 EN1 2C3 G3 G2 A1 54 A2 52 A3 51 A4 A5 49 48 A6 A7 A8 47 45 44 A9 A10 43 42 A11 41 A12 40 A13 A14 38 37 A15 A16 A17 36 34 33 A18 31 3D 1 1 3 Y1 5 Y2 6 Y3 8 9 Y4 Y5 10 12 ...


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