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74AVC16836

NXP
Part Number 74AVC16836
Manufacturer NXP
Description 20-bit registered driver
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74AVC16836 20-bit registered driver with inverted register enable (3-State) Preliminary specificati...
Datasheet PDF File 74AVC16836 PDF File

74AVC16836
74AVC16836

Overview
INTEGRATED CIRCUITS 74AVC16836 20-bit registered driver with inverted register enable (3-State) Preliminary specification Replaces datasheet 74AVC16836/74AVCH16836 dated 1998 Dec 07 1999 Jul 23 Philips Semiconductors Philips Semiconductors Preliminary specification 20-bit registered driver with inverted register enable (3-State) 74AVC16836 FEATURES • Wide supply voltage range of 1.
2 V to 3.
6 V • Complies with JEDEC standard no.
8-1A/5/7.
• CMOS low power consumption • Input/output tolerant up to 3.
6 V • DCO (Dynamic Controlled Output) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation PIN CONFIGURATION OE Y0 Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CP A0 A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 A19 LE • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • Power off disables 74AVC16836 outputs, permitting Live Insertion DESCRIPTION The 74AVC16836 is a 20-bit universal bus driver.
Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).
This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.
See the graphs on page 8 for typical curves.
Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 Y19 NC SH00159 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.
0 ns; CL = 30 pF.
PARAMETER SYMBOL tPHL/tPLH Propagation delay An to Yn Propagation delay LE to Yn; CP to Yn Input capacitance Power dissipation dissi ation capacitance ca acitance per er buffer VI = GND...


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