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74AVC16836A

nexperia
Part Number 74AVC16836A
Manufacturer nexperia
Description 20-bit registered driver
Published Jul 23, 2019
Detailed Description 74AVC16836A 20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state Rev. 6 — 2...
Datasheet PDF File 74AVC16836A PDF File

74AVC16836A
74AVC16836A

Overview
74AVC16836A 20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state Rev.
6 — 24 September 2018 Product data sheet 1.
General description The 74AVC16836A is a 20-bit universal bus driver.
Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).
This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.
See Fig.
5 for typical curves.
2.
Features and benefits • Wide supply voltage range from 1.
2 V to 3.
6 V • Complies with JEDEC standards: • JESD8-7 (1.
2 V to 1.
95 V) • JESD8-5 (1.
8 V to 2.
7 V) • JESD8-1A (2.
7 V to 3.
6 V) • CMOS low power consumption • Input/output tolerant up to 3.
6 V • Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation • Low inductance multiple VCC and GND pins to minimize noise and ground bounce • Power off disables 74AVC16836A outputs, permitting Live Insertion • Integrated input diodes to minimize input overshoot and undershoot 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74AVC16836ADGG -40 °C to + 85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.
1 mm Version SOT364-1 Nexperia 74AVC16836A 20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state 4.
Functional diagram OE CP LE A1 D LE CP Fig.
1.
Logic diagram Y1 aaa-026917 OE 1 CP 56 LE 29 A1 55 A2 54 A3 52 A4 51 A5 49 A6 48 A7 47 A8 45 A9 44 A10 43 A11 42 A12 41 A13 40 A14 38 A15 37 A16 36 A17 34 A18 33 A19 31 A20 30 EN1 2C3 C3 G2 3D 1 1 Fig.
2.
Logic symbol (IEEE/IEC) VCC 2 Y1 3 Y2 5 Y3 6 Y4 8 Y5 9 Y6 1...


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