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ZL30407

Zarlink Semiconductor Inc
Part Number ZL30407
Manufacturer Zarlink Semiconductor Inc
Description SONET/SDH Network Element PLL
Published Apr 16, 2005
Detailed Description ZL30407 SONET/SDH Network Element PLL Data Sheet Features • • • • • • • • • Meets requirements of GR-253 for SONET Strat...
Datasheet PDF File ZL30407 PDF File

ZL30407
ZL30407


Overview
ZL30407 SONET/SDH Network Element PLL Data Sheet Features • • • • • • • • • Meets requirements of GR-253 for SONET Stratum 3 and SONET Minimum Clocks (SMC) Meets requirements of GR-1244 for Stratum 3 Meets requirements of G.
813 Option 1 and 2 for SDH Equipment Clocks (SEC) Generates clocks for ST-BUS, DS1, DS2, DS3, OC-3, E1, E3, STM-1 and 19.
44 MHz Holdover accuracy of 4x10 -12 meets GR-1244 Stratum 3E and ITU-T G.
812 requirements Continuously monitors both references for frequency accuracy exceeding ±12 ppm Provides “hit-less” reference switching Compensates for Master Clock Oscillator accuracy Automatically detects frequency of both reference clocks and synchronizes to any combination of 8 kHz, 1.
544 MHz, 2.
048 MHz and 19.
44 MHz reference frequencies Allows Hardware or Microprocessor control Pin compatible with ZL30410, ZL30402 and MT90401 Ordering Information Z L30407QCC ZL30407QCC1 80 Pin LQFP Trays 80 Pin LQFP* Trays November 2004 *Pb Free Matte Tin -40°C to +85 °C Applications • • Synchronization for SDH and SONET Network Elements Clock generation for ST-BUS and GCI backplanes Description The ZL30407 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems.
In addition, it generates multiple clocks for legacy PDH equipment and provides timing for STBUS and GCI backplanes.
• • VDD GND C20i FCS OE PRI PRIOR Primary Acquisition PLL Master Clock Frequency Calibration APLL MUX SEC SECOR RefSel HW RESET Core PLL Clock Synthesizer Secondary Acquisition PLL C155P/N C34/C44 C19o C16o C8o C6o C4o C2o C1.
5o F16o F8o F0o E3DS3/OC3 E3/DS3 Microport Control State Machine JTAG IEEE 1149.
1a Tclk Tdi Tdo Tms Trst CS DS R/W A0-A6 D0-D7 MS1 MS2 RefAlign LOCK HOLDOVER R1-17 Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc.
All Rights Reserved.
ZL30407 Data Sheet The ZL3...



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