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ZL30410

Part Number	ZL30410
Manufacturer	Zarlink Semiconductor
Description	Multi-service Line Card PLL
Published	Jan 31, 2007
Detailed Description	www.DataSheet4U.com ZL30410 Multi-service Line Card PLL Data Sheet Features • • • • • Generates clocks for OC-3, STM-1,...
Datasheet	ZL30410 PDF File

Overview

www.
DataSheet4U.
com ZL30410 Multi-service Line Card PLL Data Sheet Features • • • • • Generates clocks for OC-3, STM-1, DS3, E3, DS2, DS1, E1, 19.
44 MHz and ST-BUS Meets jitter generation requirements for STM-1, OC-3, DS3, E3, J2 (DS2), E1 and DS1 interfaces Compatible with GR-253-CORE SONET stratum 3 and G.
813 SEC timing compliant clocks Provides “hit-less” reference switching Detects frequency of both reference clocks and synchronizes to any combination of 8 kHz, 1.
544 MHz, 2.
048 MHz and 19.
44 MHz reference frequencies Continuously monitors both references for frequency accuracy exceeding ±12 ppm Holdover accuracy of 70x10 -12 meets GR-1244 Stratum 3E and ITU-T G.
812 requirements Meets requirements of G.
813 Option 1 for SDH Equipment Clocks (SEC) and GR-1244 for Stratum 4E and Stratum 4 Clocks 3.
3V power supply Ordering Information ZL30410QCC 80 Pin LQFP November 2003 -40°C to 85° C • Clock generation for ST-BUS and GCI timing Description The ZL30410 is a Multi-service Line Card Phase-Locked Loop designed to generate multiple clocks for SONET, SDH and PDH equipment including timing for ST-BUS and GCI interfaces.
The ZL30410 operates in NORMAL (LOCKED), HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter and interruptions to the reference signals, the generated clocks meet international standards.
The filtering characteristics of the PLL are hardware pin selectable and they do not require any external adjustable components.
The ZL30410 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation.
• • • • Applications • • Line Card synchronization for SDH, SONET, DS3, E3, J2 (DS2), E1 and DS1 interfaces Timing card synchronization for SDH and PDH Network Elements VDD GND C20i FCS OE PRI PRIOR Primary Acquisition PLL Master Clock Frequency Calibration APLL MUX SEC SECOR RefSel RESET Core PLL Clock Synthesizer Secondary Acquisition PLL C155P/N C34/C44 C19o C16o C8o C6o C4o C2o C1.
5o F16o...

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