MOSFET. FDMS86202 Datasheet

FDMS86202 Datasheet PDF, Equivalent


Part Number

FDMS86202

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 7 Pages
PDF Download
Download FDMS86202 Datasheet PDF


FDMS86202 Datasheet
July 2014
FDMS86202
N-Channel Shielded Gate PowerTrench® MOSFET
120 V, 64 A, 7.2 mΩ
Features
„ Shielded Gate MOSFET Technology
„ Max rDS(on) = 7.2 mΩ at VGS = 10 V, ID = 13.5 A
„ Max rDS(on) = 10.3 mΩ at VGS = 6 V, ID = 11.5 A
„ Advanced Package and Silicon combination for low rDS(on)
and high efficiency
„ MSL1 robust package design
„ 100% UIL tested
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
Application
„ DC-DC Conversion
„ RoHS Compliant
Top
Pin 1
Bottom
S Pin 1
S
S
G
S
S
D
D
D
D
D
D
SD
GD
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
-Pulsed
TC = 25 °C
TA = 25 °C
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 4)
(Note 3)
(Note 1a)
Ratings
120
±20
64
13.5
240
600
156
2.7
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
0.8
45
°C/W
Device Marking
FDMS86202
Device
FDMS86202
Package
Power 56
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
©2013 Fairchild Semiconductor Corporation
FDMS86202 Rev. C3
1
www.fairchildsemi.com

FDMS86202 Datasheet
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250 μA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
VDS = 96 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
120 V
103 mV/°C
1
±100
μA
nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Static Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250 μA
ID = 250 μA, referenced to 25 °C
VGS = 10 V, ID = 13.5 A
VGS = 6 V, ID = 11.5 A
VGS = 10 V, ID = 13.5 A,TJ = 125 °C
VDS = 5 V, ID = 13.5 A
2.0
3.1 4.0
V
-10 mV/°C
6.0
8.1
10.9
44
7.2
10.3
13.2
mΩ
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
VDS = 60 V, VGS = 0 V,
f = 1 MHz
3195 4250
pF
449 600 pF
17 30 pF
0.1 0.9 2.7
Ω
Switching Characteristics
td(on)
tr
td(off)
tf
Qg
Qg
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VDD = 60 V, ID = 13.5 A,
VGS = 10 V, RGEN = 6 Ω
VGS = 0 V to 10 V
VGS = 0 V to 6 V
VDD = 60 V,
ID = 13.5 A
21
6
27
5
45
29
14.3
8.7
33
13
44
11
64
41
ns
ns
ns
ns
nC
nC
nC
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 2.1 A
VGS = 0 V, IS = 13.5 A
(Note 2)
(Note 2)
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
IF = 13.5 A, di/dt = 100 A/μs
0.69
0.76
73
117
1.2
1.3
118
187
V
ns
nC
Notes:
1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a) 45 °C/W when mounted on a
1 in2 pad of 2 oz copper
b) 115 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 600 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 20 A, VDD = 120 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 65 A.
4. Pulse Id limited by junction temperature, td 100 μs, please refer to SOA curve for more details.
©2013 Fairchild Semiconductor Corporation
FDMS86202 Rev. C3
2
www.fairchildsemi.com


Features Datasheet pdf FDMS86202 N-Channel Shielded Gate PowerT rench® MOSFET July 2014 FDMS86202 N- Channel Shielded Gate PowerTrench® MOS FET 120 V, 64 A, 7.2 mΩ Features „ S hielded Gate MOSFET Technology „ Max r DS(on) = 7.2 mΩ at VGS = 10 V, ID = 13 .5 A „ Max rDS(on) = 10.3 mΩ at VGS = 6 V, ID = 11.5 A „ Advanced Package a nd Silicon combination for low rDS(on) and high efficiency „ MSL1 robust pack age design „ 100% UIL tested General Description This N-Channel MOSFET is pr oduced using Fairchild Semiconductor’ s advanced PowerTrench® process that i ncorporates Shielded Gate technology. T his process has been optimized for the on-state resistance and yet maintain su perior switching performance. Applicati on „ DC-DC Conversion „ RoHS Complia nt Top Pin 1 Bottom S Pin 1 S S G S S D D D D D D SD GD Power 56 MOSFE T Maximum Ratings TA = 25 °C unless ot herwise noted Symbol VDS VGS ID EAS PD TJ, TSTG Parameter Drain to Source V oltage Gate to Source Voltage Drain Current -Continuous -Cont.
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