October 1997
FDV302P Digital FET, P-Channel
General Description
This P-Channel logic level enhancement mode field effect
transistor is produced using Fairchild's proprietary, high cell density, DMOS technology.
This very high density process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage applications as a replacement for digital
transistors.
Since bias resistors are not required, this one P-channel FET can replace several digital
transistors with different bias resistors such as the DTCx and DCDx series.
Features
-25 V, -0.
12 A continuous, -0.
5 A Peak.
RDS(ON) = 13 Ω @ VGS= -2.
7 V RDS(ON) = 10 Ω @ VGS = -4.
5 V.
Very low leve...